The present invention relates to a BiMOS logical circuit, and more particularly to a BiMOS logical circuit including bipolar transistors at its output stage.
Recently, logic LSIs are strongly required to have large capacity and low power dissipation. Accordingly, there is a tendency that the position of CMOS transistors to meet such requirements is being increasingly elevated. The performance of the CMOS transistors has been considerably improved in recent years by making free use of fining technologies.
However, the circuits using such CMOS transistors have the serious drawback that the operating speed is slower than that of the circuits using bipolar transistors because of the small current drivability. To improve the current drivability, there may be employed a method to increase the capacity of each component. However, this method is not so effective in that the employment thereof results in an increase in the gate capacity. Such a method eventually leads to the bad effect that it runs counter to integration because the area occupation of components becomes large.
To avoid this, BiMOS logical circuits using bipolar transistors at its output stage are employed. FIG. 1 shows an example of an inverter constituted with such a BiMOS logical circuit. This inverter circuit is composed of four MOS transistors, i.e., three NMOS transistors 1, 2 and 4 and a PMOS transistor 3, and two bipolar transistors 5 and 6. An inverted signal of an input voltage V.sub.IN delivered to the input terminal 1 is output from the output terminal 0 as an output voltage V.sub.OUT. The base currents Of the bipolar transistors 5 and 6 are controlled by the MOS transistors and the bipolar transistors are used at the output stage. For this reason, the current drivability is improved and thus a fast operating speed at which the output waveform becomes sharp can be obtained.
FIG. 2 shows a conventional NAND circuit constituted by dividing the input of the circuit shown in FIG. 1 into two inputs. An output voltage V.sub.OUT is determined on the basis of two input voltages V.sub.INa and V.sub.INb delivered to two input terminals Ia and Ib. Since the number of input terminals is increased, the transistor 1 is composed of two transistors 1a and 1b and the transistor 4 is composed of two transistors 4a and 4b.
FIG. 3 shows another example of the conventional NAND circuit based on the BiMOS logical circuit. This NAND circuit is characterized in that the function of the transistors 4a and 4b is replaced by a diode 7.
One problem with the above-mentioned conventional BiMOS logical circuit is that the operating speed is slow. As previously described, by making use of the bipolar transistors at its output stage the operating speed of the BiMOS logical circuit is considerably improved as compared to that of the CMOS logical circuit. However, since a plurality of MOS gates are connected to the input terminal or terminals, the input capacity becomes large and the waveform of an input signal becomes blunted, so that the operation becomes slow. For example, three MOS gates are connected to the input terminal 1 in the inverter shown in FIG. 1. Similarly, six MOS gates are connected to the input terminals in the NAND circuit shown in FIG. 2.
Another problem therewith is that the number of circuit components considerably increases according as the number of input terminals increases. For example, it is sufficient to use four MOS transistors in the one-input type inverter shown in FIG. 1. On the contrary, seven MOS transistors are required in the two-input type NAND circuit shown in FIG. 2. Such an increase in the number of components is not preferable in that it runs counter to integration. By using the diode as in the circuit shown in FIG. 3, it is possible to reduce the number of components. However, the "L" level of the output voltage V.sub.OUT becomes higher than the ideal value by the forward voltage drop V.sub.D of the diode, giving rise to new problem that the response speed becomes slow.